You can already buy RISC-V systems today.
Milk-V
DeepComputing
framework
But the performance is really sluggish.
Yes and no. I did a lot of work profiling several SBCs with ARM, RISCV and x86 CPUs. I found that the SG2000-based Milk Duo-S had single thread performance comparable to the 1GHz ARM Wandboard Quad and Celeron-based Udoo x86 Advanced boards for general purpose tasks. The difference is that the SG2000 used 0.6 watts at idle and 0.8 watts at full power, while the WB Quad used 2.7 and 3.4 watts and 9.1 and 10.1, respectively. Another difference is that the SG2000-based Milkv Duo-S cost $13.
Of course, both the Wandboard Quad and Udoo x86 Advanced have multiple cores, and easily outperformed the single core SG2000 in multithreaded tasks. In most cases, the power use scaled with threads to the maximum core count, but less than 1:1 (it was more efficient to bring up additional cores). I did the same tests on Raptor's POWER9 Talos II systems, and obviously performance was dramatically better, and the power usage was much higher, but not like the G5 and Cell systems I tested (both used over 100 watts at full power). For comparison, I did the same tasks on a 1.25GHz Mac mini (PowerPC G4), and while performance was almost 1/3 better, it used 17.0 and 31.6 watts, respectively (and was faster than the 2.2GHz PowerMac G5 I tested).
I think the SG2000 suffers from very small i- and d-cache sizes. Multicore support would obviously be a huge benefit. What is also notable about the SG2000 is that the entire boot process can be replaced, including the firmware. This is done as part of Lup Lee's successful efforts to port NuttX to the board.
Personally, while I am a huge fan of PowerPC/POWER architectures, in my efforts to port and/or build compiler and assembler pieces for the architecture, I have become dismayed at the sheer number of instructions the CPUs support. I have been reading through the OpenPOWER specifications, and with each version new instructions are added. I feel like the "Reduced" part of RISC has been lost, and the boundary between CISC and RISC seems very blurry. I have not been privy to the conversations about the additional instructions, but I do wonder if they are truly orthogonal and if they can maintain one instruction per cycle completion. If there is evidence of stalls or synchronization issues, perhaps it would be better to let the compiler build more steps from fewer instructions.
In comparison, RISC-V sticks to a limited instruction set and maintains one instruction per cycle. Yes, there is less pipelining and yes, no SMT-type re-use of CPU resources, but that also makes for a simpler design, which makes the entire production process cheaper.
I would really like to see a fully open PowerPC/POWER SBC with a goal of making it into a laptop and cellphone, targeting human rights defenders and other groups that are increasingly targeted by authoritarian governments. Although the market size would almost certain make production units expensive, as the adage goes, freedom isn't free.
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