Show Posts

This section allows you to view all posts made by this member. Note that you can only see posts made in areas you currently have access to.


Messages - ClassicHasClass

Pages: [1] 2 3 ... 31
1
General CPU Discussion / Re: 3U HSF End of Life'd
« on: October 02, 2024, 09:21:48 pm »
Hopefully this is a sign S1 is coming out quickly, presumably with its own cooler.

2
Firmware / Re: Updating PNOR/BMC firmware on talos II Lite
« on: September 30, 2024, 10:30:33 pm »
You probably should be running the most current firmware anyway; there are other improvements. You don't need to update the FPGA, just the PNOR to get Petitboot up to date.

3
Blackbird / Re: Potential Aspeed slow failure?
« on: September 05, 2024, 11:46:52 am »
Glad to hear it self-resolved, at least.

4
Yeah, I haven't found a RISC-V system remotely in POWER9's class, let alone Power10 or (presumably) S1. So far it's a lot of sizzle and very little steak.

I wouldn't mind a Raptor RISC-V system, but I wouldn't want it to distract from whatever the nextgen OpenPOWER box is. Although I say that as a PowerPC bigot, I think I would get a lot more out of that than any RISC-V system right now.

5
Well, you kind of can: Arctic Tern is a Microwatt device. The main issue there is the expense, and it's intended as a replacement BMC instead of a cheap screw-around-with board.

6
In the meantime, the patch sets for Baseline Interpreter/Compiler in Firefox 128ESR are now available. I'm typing this in it myself and the test suites all pass, so I'm pretty confident it will work well.

https://www.talospace.com/2024/08/baseline-jit-patches-available-for.html

7
If I'm reading https://github.com/Xudong-Huang/generator-rs/blob/master/src/detail/asm/asm_riscv64_c_elf.S correctly, basically what it's asking for is a function prologue to save registers. This must obey the OpenPOWER SysV ABI, so it would be something like

mflr r0
std r0,16(r1)
mfcr r0
std r0,8(r1)
stdu r1,-FRAMESIZE(r1)

and then start saving your callee-saved registers into the frame, which is basically any non-volatile GPRs and FPRs your routine might touch.

Not quite sure what it's doing with the green task routine but I only read the source cursorily.

8
My next immediate step is to pull the JIT up to Fx128, since I'm also needing it for Github in particular (grr).

9
After a bad initial experience I reinstalled last night and Chromium has come a very long way on F40. I still got a crash - honestly about 90% sure something on Facebook triggered it - but it did successfully run Google Earth at a usable speed, and that is progress.  Looking forward to more changes, and to seeing ClassicHasClass's Firefox JIT catch up.

It's a matter of me sitting down with it. Work has been really busy lately and I haven't had time for much of anything. :/

10
I actually use R at work. Handy.

11
That gives me some point of comparison, though it may be difficult to figure out what specifically the ARM dynrec is benefiting from. But thanks for looking at it.

12
Is Rosetta checked in Get Info?

13
I'm not sure, actually. I'll have to load it up on my M1 Air and check it out. The x86_64 figure could be because those don't use dynrec, but ARM should ... unless you're running the Intel Mac build on your M2, not an Apple silicon build?

14
That version should have my fix in it, so it must be something else.

15
What was the issue with dosbox-staging? Something I should look at or do you think it's packaging-specific?

Pages: [1] 2 3 ... 31