I want to believe in this as much as anybody else here, but the only way this adds up -- and it's still quite a stretch -- is if this chip really is a Power10, possibly with
very minor metal-mask-only changes (like the spectre-fix stepping of Power9), and Raptor somehow miraculously talked IBM into this but couldn't convince them to license the "Power10" trademark. Like I said, quite a stretch.
I'd love to believe that somebody other than IBM is doing an owner-controlled, independently-developed PowerISA 3.2 chip on a leading-edge node. But that's
way into "flying pigs in snowy hell" territory. It's eight figures just for the maskset on anything newer than Power9's GloFo14 process. What sort of investor gave that kind of cash to a company which did not seem to exist until this announcement surfaced? (and can I have some?
) Not to mention the lead times! If this was an independent design with any chance of shipping by end of 2024, there would be physical MPW samples already.
I'd love to be totally wrong about all of this.
Even if it is a "white label Power10", there are still a lot of questions. What's the story with the memory controller? I saw some comment somewhere suggesting maybe putting a serial-to-parallel (OMI-to-DDR) fanout chip (the heatsinked chip in
this photo) inside the same package as the CPU die, along with an immutable ROM for its firmware. But that too seems improbable... those fanout chips are designed to drive really short traces on the same PCB (this is a big part of the power savings they claim). The odds that they would be able to drive big long traces passing across a DIMM slot and cardedge seem slim. None of the other customers buying those chips need that capability (if they did, they wouldn't be fooling around with OMI in the first place).
