Updating PNOR/BMC firmware on talos II Lite

[adaptl]

Hey all,

I'm trying to get my NAVI10 AMDGPU to work with my Talos II lite. I've got the firmware in BOOTKERNFW. Just not sure if that requires an up-to-date PNOR cause this PNOR/BMC is from 2018. Just wondering if I need to update the PNOR to a more modern one to get the firmware to load.

I went on a major month-long mission bricking and re-flashing the BMC/PNOR to discover that my system won't work with the new PNOR/BMC, I even had to get a CH341a to flash it manually. Maybe this is because it's a special developer system with DD2.1-stepped CPU?. Also, I can't build the old version of OpenBMC due to bitbake having fetch issues with github.com, so it's not like I could patch BMC/PNOR myself which sucks, I guess I could bisect the code and figure it out but that would be like 50+ hours of work.

Maybe the solution for me is just to use coreboot or HEADS or something simpler. Does anyone know what the state of that is?

[ClassicHasClass]

You probably should be running the most current firmware anyway; there are other improvements. You don't need to update the FPGA, just the PNOR to get Petitboot up to date.

[bobpaul]

I built one of the v1.xx BMC firmwares about a year ago. I might still have notes on that, but it involved switching a lot of the repo urls in bitbake packages. All the source is still online, just not at the same URLs.

You can find Raptor's Repos on

• https://git.raptorcs.com/git/
• https://git.raptorengineering.com/git/
• https://gitlab.raptorengineering.com/

and at some point in time they moved some repos from one server to another.

Maybe this is because it's a special developer system with DD2.1-stepped CPU?

Do you know what part number your CPU is?

Edit: Oh, I see from your other thread and IRC that you it's the same 02AA883 CPU I have. I already mentioned on IRC, but I'm going to repeat here just so it's searchable by others: aside from "just" being DD2.1 stepping, this CPU uses unpaired cores. At least for adaptl and myself, all 4 of the active cores are on the same quad even (cores 0x14, 0x15, 0x16, and 0x17 are the active cores). All of the production (DD2.2+) 4 core CPUs were made for RaptorCS and only made from dies that had 4 usable cores which weren't paired (so ie, if core 0x14 and 0x15 were good, only one was used). The big ramification is L2 and L3 cache sharing which would worsen the spectre/meltdown concerns.

Here's the core layout in the Sforza CPUs (pg37). (core 0x00 from linux's perspective has address 0x20 on the diagram)


I wasn't sure if all of the DD2.1 special developer systems were the same or if some had unpaired cores.