Bonus cache! Presumably 1 core in each of the pair that share the L2/L3 was bad in some way, and that die did not have enough paired-cache cores to make a matched set of 18, so used some of the remaining unpaired cores to make up the difference. Given the difficulty of yielding big die on a modern technology node, reducing core count is common industry practice. It's a little unusual here that 2 core share the cache so when one gets knocked out, the other retains access to the full amount of cache. If the cache had been reduced any, then that core might perform worse versus the same workload on only 1 of the 2 cores in a paired-cache config, so it gets to keep the full local cache without having to share any...yay!
Raptor identifies this config specifically as "unpaired" in their 4-core and 8-core cpu description, e.g.:
https://raptorcs.com/content/CP9M31/intro.html 4 cores per package
3.2GHz base / 3.8GHz turbo (WoF)
90W TDP
All Core Turbo capable
32KB L1 data cache + 32KB L1 instruction cache / core
512KB unpaired L2 cache / core 10MB unpaired L3 cache / coreVersus the larger core-count, e.g.:
https://raptorcs.com/content/CP9M36/intro.html 18 cores per package
2.8GHz base / 3.8GHz turbo (WoF)
190W TDP
32KB L1 data cache + 32KB L1 instruction cache / core
512KB L2 cache / core pair 10MB L3 cache / core pairIf you don't want the bonus cache, I am sure someone would trade CPUs with you. ;-)
