General OpenPOWER Hardware > General CPU Discussion

Asymmetric CPUs with the Same Core Count

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ClassicHasClass:
Do you mean the timebase register? Not equivalent with the time-stamp counter on x86(_64) but should be usable for similar purposes.

https://www.gnu.org/software/libc/manual/html_node/PowerPC.html

amock:

--- Quote from: ClassicHasClass on October 01, 2022, 01:12:02 pm ---Do you mean the timebase register? Not equivalent with the time-stamp counter on x86(_64) but should be usable for similar purposes.

https://www.gnu.org/software/libc/manual/html_node/PowerPC.html

--- End quote ---
Yes, thanks.  I couldn't remember the name but it looks to be easy to use and good enough.

ejfluhr:
500MHz affords 1/500Mhz = 2ns resolution of latency?   Sounds cool!   What is same-die typical memory latency, ~70ns??   Local L3 would have to run on the order of ~10ns??

There could be sensitivity to core frequency, presuming the L3 cache and some of the internal transfer network is pipelined.  E.g. running at 3.8GHz turbo will give a better answer than 2.8GHz base.

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